Accuracy of integrators and sample-and-hold circuits including conventional switched capacitor circuits depends on gain of inverting amplifiers included in the switched capacitor circuits. However, since high gain amplifiers generally have the drawbacks of high current consumption and low operation speed, power consumption and operation speed problems are involved in using such high gain amplifiers to increase accuracy of integrators and sample-and-hold circuits.
There has been proposed a technique to provide a high-speed inverting amplifier which includes an inverter as an amplifier in Non-Patent Literature (NPL) 1. An inverter amplifier is capable of driving at a large current during nonlinear operation, and is therefore suitable as a high speed inverting amplifier. However, the gain of the inverter amplifier is 30 dB at most. An integrator or a sample-and-hold circuit including the inverter amplifier cannot achieve high accuracy alone.
In NPL 2, a technique of correlated level shifting (hereinafter referred to as CLS) is proposed to address the problem. For example, in an integration circuit or a sample-and-hold circuit to which the technique of CLS is applied, a compensation capacitor connected in parallel with a storage capacitor is charged, and is then connected in series between an amplifier output terminal and an integration capacitor, so that the output voltage of the integration circuit or the sample-and-hold circuit has a “raised level” (upward level shift). In this case, the bottom level of the voltage (shifted upward) at an output terminal of the amplifier is substantially equal to the voltage level in an autofeedback state, so that input-referred offset due to output fluctuation is minimized. Accordingly, the proposed integrator with a low gain amplifier using the technique of CLS operates as accurate as an integrator with a high gain amplifier.
FIG. 26 illustrates a configuration of a conventional switched capacitor circuit disclosed in NPL 2. The switched capacitor circuit disclosed in FIG. 26 functions as a two-fold amplifier in which the technique of CLS is used. The switched capacitor circuit includes capacitors 1001, 1002, and 1004, an operational amplifier 1003, switches 1005, 1006, 1007, and 1008, a reference voltage source 1009, an input terminal 1010, and an output terminal 1011. The switched capacitor circuit in operation transits from a sampling phase to a transfer phase to a CLS phase in this order according to ON-OFF control of the switches. These phases of the switched capacitor circuit never overlap each other at any time. The following describes operation of the switched capacitor circuit in each of the phases.
FIG. 27A, FIG. 27B, and FIG. 27C are circuit diagrams illustrating connection in the switched capacitor circuit disclosed in NPL 2 in the sampling phase, transfer phase, and CLS phase, respectively.
As illustrated in FIG. 27A, in the sampling phase, the switches 1005 and 1006 are connected to the input terminal 1010, the switch 1007 is closed, one of the switches 1008 connects the reference voltage source 1009 and the capacitor 1004, and the other of the switches 1008 connects the output port of the operational amplifier 1003 and the output terminal 1011. With this connection, the capacitor 1001 stores a charge of C·Vin [C] with an electrode on the left side in FIG. 27A being a positive electrode, where the voltage at the input terminal 1010 is Vin [V] and the reference voltage of the reference voltage source 1009 is 0 [V]. At the same time, the capacitor 1002 stores a charge of C·Vin [C] with an electrode on the right side in FIG. 27A being a positive electrode.
In the transfer phase following the sampling phase, as illustrated in FIG. 27B, the switch 1005 is connected to the reference voltage source 1009, the switch 1006 is connected to the output terminal 1011, the switch 1007 is open, and the connection of the switches 1008 are maintained. With this connection, transfer of the charge stored in the capacitor 1001 to the capacitor 1002 starts. In other words, the voltage across the capacitor 1002 increases toward 2 Vin [V]. Furthermore, the operational amplifier 1003 drives the capacitor 1004, so that the voltage across the capacitor 1004 also increases toward 2 Vin [V].
However, when the gain of the operational amplifier 1003 is insufficient, the voltage at the negative input terminal of the operational amplifier 1003 (that is, the virtual ground voltage of the system) floats. Thus, not the whole charge of the capacitor 1001 is transferred to the capacitor 1002, and the voltage at the output terminal 1011 does not reach 2 Vin [V]. Such insufficient increase of the voltage at the output terminal 1011 is caused by a large difference of voltage at the output port of the operational amplifier 1003 (approximately 2 Vin [V]) from the virtual ground voltage (equal to the voltage of the reference voltage source 1009).
In the CLS phase following the transfer phase, as illustrated in FIG. 27C, the connection or disconnection of each of the switches 1005, 1006, and 1007 is maintained, and the one of the switches 1008 connects the output port of the operational amplifier 1003 and the capacitor 1004, and the other of the switches 1008 is open. With this connection, the capacitor 1004 is connected between the output port of the operational amplifier 1003 and the output terminal 1011. The voltage across the capacitor 1004 is approximately 2 Vin [V], which produces the “level-raising” effect (level-shifting effect) and thereby the voltage at the output port of the operational amplifier 1003 changes from approximately 2 Vin [V] to a level substantially equal to the voltage of the reference voltage source 1009 (=0 V). With this, the floating of the voltage at the negative input port of the operational amplifier 1003 (equal to the virtual ground voltage of the system) is significantly reduced, so that the charge of the capacitor 1001 is substantially completely transferred to the capacitor 1002. As a result, the voltage across the capacitor 1002 becomes substantially equal to 2 Vin, so that the switched capacitor circuit achieves accurate two-fold amplification even where the gain of the operational amplifier included in the switched capacitor circuit is low.